1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices, and, more particularly, to a multi-stage epi process for forming semiconductor devices, and the resulting device.
2. Description of the Related Art
Manufacturing semiconductor devices is a very complex, cost-intensive, and competitive industry. Manufacturing a semiconductor device may involve performing hundreds of individual process steps, such as forming layers of materials, selectively removing portions of those layers of materials, implanting dopant atoms into various structures on the substrate and performing various heat treatment processes. Such steps are combined in any of a vast variety of different process flows to produce semiconductor devices that function in the desired manner.
The semiconductor manufacturing industry is very competitive in that there is a constant drive to reduce the unit cost of semiconductor devices and to increase product yields. Thus, there is constant pressure to develop new and improved processes for manufacturing semiconductor devices so that product yields may be increased and/or costs may be reduced. For example, in the case of high voltage bipolar devices that are isolated by trench isolation regions, the manufacturing of such devices can be quite complex. Such processes typically involve performing an ion implant process into a bulk substrate to thereby form a buried sub-collector layer. Subsequent fabrication involves performing multiple epitaxial deposition steps to form multiple layers of epitaxial silicon at various stages during the course of the manufacture of the device.
Moreover, in some cases, trench isolation regions used to isolate a semiconductor device have very high aspect ratios, i.e., the ratio of trench depth to trench width, for example on the order of approximately 25–30. In forming such trench isolation regions, it is often necessary to perform a so-called channel stop implant step in an effort to introduce dopant materials into the substrate adjacent the bottom of the previously formed trench. The channel stop implant serves a variety of purposes, e.g., preventing latch-up, tub-to-tub leakage, cross-talk, etc. However, in modem devices that have isolation trenches with very high aspect ratios, e.g., high voltage devices, it is very difficult to properly introduce the desired dopant material at the bottom of such a trench. More specifically, two problems may arise. First, there may be inadequate dopant material placed in the substrate adjacent the bottom of the trench, thereby leading to the problems identified above, e.g., latch-up, cross-talk, etc. If the dopant dose of the ion implant process is increased to insure that dopant material is present in the substrate adjacent the bottom of the trench, then, due to the high aspect ratio, excessive amounts of dopant material penetrate the sidewalls of the trench leading to other problems, e.g., increased consumption of plot space, poor electrical performance, etc.
In view of the foregoing, there is a need for an improved methodology for forming semiconductor devices that may improve product yields, reduce costs and increase overall manufacturing efficiency. The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.